//////////////////////////////////////////////////////////////////////
////                                                              ////
////  DCMClockFix.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the "Pico E12" project                 ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2005, Pico Computing, INC.                     ////
//// http://www.picocomputing.com                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////////////////////////////////////////////////////////////////////JF
//This module is necessary to keep the DCMs running at the maximum speed specified in the datasheets
//This is really only necessary for engineering sample devices, but it doesn't hurt anything.

`include "PicoDefines.v"
`timescale 10ns / 1ps

module DCMClockFix(ClockIn, DCMKeeper);

input ClockIn;
output DCMKeeper;

wire ClockIn;

wire DividedClock;                                             //This signal is a 1.5 MHz Clock
wire DividedClockLink;

wire DCMKeeper;

                                                               //These SRL16's take the external 50 MHz clock and turn it into a ~1.5 MHz clock
SRL16 ClockDivider1(.Q(DividedClock), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(ClockIn), .D(DividedClockLink)); 
SRL16 ClockDivider2(.Q(DividedClockLink), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(ClockIn), .D(DividedClock));
//synthesis attribute INIT of ClockDivider1 is "FFFF";
//synthesis attribute INIT of ClockDivider2 is "0000";

`ifdef DISABLE_DCM1
//DCM #1
//-----------------------------DCM Primitive------------------------------//
wire DCM1ClockOut;
DCM_ADV CLOCK_DCM1(.CLKFB(),                                          //Phase control feedback is not used for this clock
                  .CLKIN(DividedClock),                               //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(1'b0),                                         //Reset Signal
                  .CLKDV(),
                  .CLKFX(),
                  .CLKFX180(),
                  .CLK0(DCM1ClockOut),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
                  .LOCKED(),
						.PSDONE());


//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM1 is "NONE";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM1 is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM1 is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM1 is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM1 is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM1 is "MAX_RANGE";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM1 is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM1 is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM1 is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM1 is "FALSE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM1 is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM1 is "FALSE";
//synthesis attribute FACTORY_JF of CLOCK_DCM1 is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM1.CLK_FEEDBACK = "NONE";
defparam CLOCK_DCM1.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM1.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM1.CLKIN_PERIOD = "20";
defparam CLOCK_DCM1.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM1.DCM_PERFORMANCE_MODE = "MAX_RANGE";
defparam CLOCK_DCM1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM1.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM1.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM1.DUTY_CYCLE_CORRECTION = "FALSE";
defparam CLOCK_DCM1.PHASE_SHIFT = "0";
defparam CLOCK_DCM1.STARTUP_WAIT = "FALSE";
defparam CLOCK_DCM1.FACTORY_JF = "F0F0";		 
//synthesis translate_on

`endif



`ifdef DISABLE_DCM2
//DCM #2
//-----------------------------DCM Primitive------------------------------//
wire DCM2ClockOut;
DCM_ADV CLOCK_DCM2(.CLKFB(),                                          //Phase control feedback is not used for this clock
                  .CLKIN(DividedClock),                               //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(1'b0),                                         //Reset Signal
                  .CLKDV(),
                  .CLKFX(),
                  .CLKFX180(),
                  .CLK0(DCM2ClockOut),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
                  .LOCKED(),
						.PSDONE());


//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM2 is "NONE";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM2 is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM2 is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM2 is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM2 is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM2 is "MAX_RANGE";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM2 is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM2 is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM2 is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM2 is "FALSE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM2 is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM2 is "FALSE";
//synthesis attribute FACTORY_JF of CLOCK_DCM2 is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM2.CLK_FEEDBACK = "NONE";
defparam CLOCK_DCM2.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM2.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM2.CLKIN_PERIOD = "20";
defparam CLOCK_DCM2.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM2.DCM_PERFORMANCE_MODE = "MAX_RANGE";
defparam CLOCK_DCM2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM2.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM2.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM2.DUTY_CYCLE_CORRECTION = "FALSE";
defparam CLOCK_DCM2.PHASE_SHIFT = "0";
defparam CLOCK_DCM2.STARTUP_WAIT = "FALSE";
defparam CLOCK_DCM2.FACTORY_JF = "F0F0";		 
//synthesis translate_on

`endif




`ifdef DISABLE_DCM3
//DCM #3
//-----------------------------DCM Primitive------------------------------//
wire DCM3ClockOut;
DCM_ADV CLOCK_DCM3(.CLKFB(),                                           //Phase control feedback is not used for this clock
                  .CLKIN(DividedClock),                               //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(1'b0),                                         //Reset Signal
                  .CLKDV(),
                  .CLKFX(),
                  .CLKFX180(),
                  .CLK0(DCM3ClockOut),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
                  .LOCKED(),
						.PSDONE());


//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM3 is "NONE";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM3 is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM3 is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM3 is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM3 is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM3 is "MAX_RANGE";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM3 is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM3 is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM3 is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM3 is "FALSE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM3 is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM3 is "FALSE";
//synthesis attribute FACTORY_JF of CLOCK_DCM3 is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM3.CLK_FEEDBACK = "NONE";
defparam CLOCK_DCM3.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM3.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM3.CLKIN_PERIOD = "20";
defparam CLOCK_DCM3.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM3.DCM_PERFORMANCE_MODE = "MAX_RANGE";
defparam CLOCK_DCM3.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM3.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM3.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM3.DUTY_CYCLE_CORRECTION = "FALSE";
defparam CLOCK_DCM3.PHASE_SHIFT = "0";
defparam CLOCK_DCM3.STARTUP_WAIT = "FALSE";
defparam CLOCK_DCM3.FACTORY_JF = "F0F0";		 
//synthesis translate_on

`endif




`ifdef DISABLE_DCM4
//DCM #4
//-----------------------------DCM Primitive------------------------------//
wire DCM4ClockOut;
DCM_ADV CLOCK_DCM4(.CLKFB(),                                           //Phase control feedback is not used for this clock
                  .CLKIN(DividedClock),                               //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(1'b0),                                         //Reset Signal
                  .CLKDV(),
                  .CLKFX(),
                  .CLKFX180(),
                  .CLK0(DCM4ClockOut),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
                  .LOCKED(),
						.PSDONE());

//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM4 is "NONE";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM4 is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM4 is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM4 is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM4 is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM4 is "MAX_RANGE";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM4 is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM4 is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM4 is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM4 is "FALSE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM4 is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM4 is "FALSE";
//synthesis attribute FACTORY_JF of CLOCK_DCM4 is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM4.CLK_FEEDBACK = "NONE";
defparam CLOCK_DCM4.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM4.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM4.CLKIN_PERIOD = "20";
defparam CLOCK_DCM4.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM4.DCM_PERFORMANCE_MODE = "MAX_RANGE";
defparam CLOCK_DCM4.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM4.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM4.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM4.DUTY_CYCLE_CORRECTION = "FALSE";
defparam CLOCK_DCM4.PHASE_SHIFT = "0";
defparam CLOCK_DCM4.STARTUP_WAIT = "FALSE";
defparam CLOCK_DCM4.FACTORY_JF = "F0F0";		 
//synthesis translate_on

`endif


`ifdef DISABLE_DCM5
//DCM #5
//-----------------------------DCM Primitive------------------------------//
wire DCM5ClockOut;
DCM_ADV CLOCK_DCM5(.CLKFB(),                                           //Phase control feedback is not used for this clock
                  .CLKIN(DividedClock),                               //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(1'b0),                                         //Reset Signal
                  .CLKDV(),
                  .CLKFX(),
                  .CLKFX180(),
                  .CLK0(DCM5ClockOut),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
                  .LOCKED(),
						.PSDONE());

//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM5 is "NONE";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM5 is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM5 is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM5 is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM5 is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM5 is "MAX_RANGE";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM5 is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM5 is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM5 is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM5 is "FALSE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM5 is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM5 is "FALSE";
//synthesis attribute FACTORY_JF of CLOCK_DCM5 is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM5.CLK_FEEDBACK = "NONE";
defparam CLOCK_DCM5.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM5.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM5.CLKIN_PERIOD = "20";
defparam CLOCK_DCM5.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM5.DCM_PERFORMANCE_MODE = "MAX_RANGE";
defparam CLOCK_DCM5.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM5.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM5.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM5.DUTY_CYCLE_CORRECTION = "FALSE";
defparam CLOCK_DCM5.PHASE_SHIFT = "0";
defparam CLOCK_DCM5.STARTUP_WAIT = "FALSE";
defparam CLOCK_DCM5.FACTORY_JF = "F0F0";		 
//synthesis translate_on

`endif




`ifdef DISABLE_DCM6
//DCM #6
//-----------------------------DCM Primitive------------------------------//
wire DCM6ClockOut;
DCM_ADV CLOCK_DCM6(.CLKFB(),                                           //Phase control feedback is not used for this clock
                  .CLKIN(DividedClock),                               //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(1'b0),                                         //Reset Signal
                  .CLKDV(),
                  .CLKFX(),
                  .CLKFX180(),
                  .CLK0(DCM6ClockOut),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
                  .LOCKED(),
						.PSDONE());


//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM6 is "NONE";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM6 is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM6 is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM6 is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM6 is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM6 is "MAX_RANGE";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM6 is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM6 is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM6 is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM6 is "FALSE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM6 is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM6 is "FALSE";
//synthesis attribute FACTORY_JF of CLOCK_DCM6 is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM6.CLK_FEEDBACK = "NONE";
defparam CLOCK_DCM6.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM6.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM6.CLKIN_PERIOD = "20";
defparam CLOCK_DCM6.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM6.DCM_PERFORMANCE_MODE = "MAX_RANGE";
defparam CLOCK_DCM6.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM6.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM6.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM6.DUTY_CYCLE_CORRECTION = "FALSE";
defparam CLOCK_DCM6.PHASE_SHIFT = "0";
defparam CLOCK_DCM6.STARTUP_WAIT = "FALSE";
defparam CLOCK_DCM6.FACTORY_JF = "F0F0";		 
//synthesis translate_on

`endif




`ifdef DISABLE_DCM7
//DCM #7
//-----------------------------DCM Primitive------------------------------//
wire DCM7ClockOut;
DCM_ADV CLOCK_DCM7(.CLKFB(),                                           //Phase control feedback is not used for this clock
                  .CLKIN(DividedClock),                               //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(1'b0),                                         //Reset Signal
                  .CLKDV(),
                  .CLKFX(),
                  .CLKFX180(),
                  .CLK0(DCM7ClockOut),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
                  .LOCKED(),
						.PSDONE());

//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM7 is "NONE";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM7 is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM7 is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM7 is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM7 is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM7 is "MAX_RANGE";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM7 is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM7 is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM7 is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM7 is "FALSE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM7 is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM7 is "FALSE";
//synthesis attribute FACTORY_JF of CLOCK_DCM7 is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM7.CLK_FEEDBACK = "NONE";
defparam CLOCK_DCM7.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM7.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM7.CLKIN_PERIOD = "20";
defparam CLOCK_DCM7.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM7.DCM_PERFORMANCE_MODE = "MAX_RANGE";
defparam CLOCK_DCM7.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM7.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM7.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM7.DUTY_CYCLE_CORRECTION = "FALSE";
defparam CLOCK_DCM7.PHASE_SHIFT = "0";
defparam CLOCK_DCM7.STARTUP_WAIT = "FALSE";
defparam CLOCK_DCM7.FACTORY_JF = "F0F0";		 
//synthesis translate_on

`endif




`ifdef DISABLE_DCM8
//DCM #8
//-----------------------------DCM Primitive------------------------------//
wire DCM8ClockOut;
DCM_ADV CLOCK_DCM8(.CLKFB(),                                           //Phase control feedback is not used for this clock
                  .CLKIN(DividedClock),                               //Clock Input (After Input Clock Buffer)
                  .DADDR(7'b0),                                       //Speed is constant, so all the D ports are unused
                  .DCLK(1'b0),
                  .DEN(1'b0),
                  .DI(16'b0),
                  .DWE(1'b0),
                  .PSCLK(1'b0),                                       //Phase is constant, so all the P ports are unused
                  .PSEN(1'b0),
                  .PSINCDEC(1'b0),
                  .RST(1'b0),                                         //Reset Signal
                  .CLKDV(),
                  .CLKFX(),
                  .CLKFX180(),
                  .CLK0(DCM8ClockOut),
						.CLK2X(),
						.CLK2X180(),
						.CLK90(),
						.CLK180(),
						.CLK270(),
						.DO(),
						.DRDY(),
                  .LOCKED(),
						.PSDONE());


//---------------------Other DCM Options---------------------//
//synthesis attribute CLK_FEEDBACK of CLOCK_DCM8 is "NONE";
//synthesis attribute CLKDV_DIVIDE of CLOCK_DCM8 is "2";
//synthesis attribute CLKIN_DIVIDE_BY_2 of CLOCK_DCM8 is "FALSE";
//synthesis attribute CLKIN_PERIOD of CLOCK_DCM8 is "20";
//synthesis attribute CLKOUT_PHASE_SHIFT of CLOCK_DCM8 is "NONE";
//synthesis attribute DCM_PERFORMANCE_MODE of CLOCK_DCM8 is "MAX_RANGE";
//synthesis attribute DESKEW_ADJUST of CLOCK_DCM8 is "SYSTEM_SYNCHRONOUS";
//synthesis attribute DFS_FREQUENCY_MODE of CLOCK_DCM8 is "LOW";
//synthesis attribute DLL_FREQUENCY_MODE of CLOCK_DCM8 is "LOW";
//synthesis attribute DUTY_CYCLE_CORRECTION of CLOCK_DCM8 is "FALSE";
//synthesis attribute PHASE_SHIFT of CLOCK_DCM8 is "0";
//synthesis attribute STARTUP_WAIT of CLOCK_DCM8 is "FALSE";
//synthesis attribute FACTORY_JF of CLOCK_DCM8 is "F0F0";

//synthesis translate_off
defparam CLOCK_DCM8.CLK_FEEDBACK = "NONE";
defparam CLOCK_DCM8.CLKDV_DIVIDE = "2";
defparam CLOCK_DCM8.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam CLOCK_DCM8.CLKIN_PERIOD = "20";
defparam CLOCK_DCM8.CLKOUT_PHASE_SHIFT = "NONE";
defparam CLOCK_DCM8.DCM_PERFORMANCE_MODE = "MAX_RANGE";
defparam CLOCK_DCM8.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam CLOCK_DCM8.DFS_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM8.DLL_FREQUENCY_MODE = "LOW";
defparam CLOCK_DCM8.DUTY_CYCLE_CORRECTION = "FALSE";
defparam CLOCK_DCM8.PHASE_SHIFT = "0";
defparam CLOCK_DCM8.STARTUP_WAIT = "FALSE";
defparam CLOCK_DCM8.FACTORY_JF = "F0F0";		 
//synthesis translate_on

`endif

//This logic keep the DCMs from being optimized out, despite multiple keeps
`ifdef IS_FX12
     `ifndef DISABLE_DCM4
	        assign DCMKeeper = 1'b0;
     `else
           assign DCMKeeper = (
           `ifdef DISABLE_DCM1
                 DCM1ClockOut |
           `endif
                 `ifdef DISABLE_DCM2
                 DCM2ClockOut |
           `endif
	              `ifdef DISABLE_DCM3
                 DCM3ClockOut |
           `endif
	              DCM4ClockOut);
     `endif
`endif // IS_FX12
            
`ifdef IS_LX25
     `ifndef DISABLE_DCM8
           assign DCMKeeper = 1'b0;
     `else
           assign DCMKeeper = (
          `ifdef DISABLE_DCM1
                DCM1ClockOut |
          `endif
     
          `ifdef DISABLE_DCM2
                DCM2ClockOut |
          `endif

          `ifdef DISABLE_DCM3
                DCM3ClockOut |
          `endif

          `ifdef DISABLE_DCM4
                DCM4ClockOut |
          `endif

          `ifdef DISABLE_DCM5
                DCM5ClockOut |
          `endif

          `ifdef DISABLE_DCM6
                DCM6ClockOut |
          `endif

          `ifdef DISABLE_DCM7
                DCM7ClockOut |
          `endif
          DCM8ClockOut);
     `endif
`endif // IS_LX25



endmodule